Wearable devices and devices interconnected via the emerging Internet of Things (IOTs) are currently made with surface-mount technology developed for the desktop computer and refined for mobile electronic systems (e.g., mobile phones, tablets, etc.). For instance, such technology typically utilizes FR4-based Printed Circuit Board (PCB) substrates that include multiple layers of electrical routing interconnect. FR4 is a grade designation assigned to glass-reinforced epoxy laminate sheets and PCBs. It is a composite material composed of woven fiberglass cloth with an epoxy resin binder that is Flame Resistant. Semiconductor chips are mounted on the substrate along with other discrete passive devices (e.g., resistors, capacitors).
Wearable devices should preferably be compact, light, reliable, and inexpensive. FR4-based PCB assemblies are typically 1.5-2.5 millimeters (mm) thick, are rigid, and have a large surface area. So-called “flex” or “rigid-flex” polyimide-based substrates offer greater flexibility than FR4-based PCB, but are costly and utilize the surface-area of the substrate inefficiently. FIG. 1A illustrates a wearable device utilizing a conventional flex PCB substrate. For example, substrate 101 may be a flex polyimide-based substrate that includes a surface-mounted microprocessor 103 that is interconnected to surface-mounted passive device 105. However, such flexible circuits typically made from polyimide have limited use are thicker than 200 microns (μm) and can only provide electrical traces and do not replace the PCBA.
Multi-chip packaging requires an interposer substrate to connect a memory chip stack to logic chips. Typically, the memory and logic chips are on opposite sides of a thin interposer substrate composed of silicon (Si). FIG. 1B schematically illustrates a conventional 3D multi-chip packaging. As shown, IC die 111 is mounted on substrate 113 at solder balls 115. Stacked memory chips 117 are interconnected by trans-silicon vias (TSV) 119 and are mounted on logic chip 121. Interposer 123 interconnects IC die 111 to logic chip 121.
Desirable characteristics of the interposer include excellent signal integrity, high reliability, and low cost. Si-based interposers are costly and also suffer from reliability issues at thicknesses smaller than 250 μm. Alternatives such as glass have been proposed, but these also suffer from reliability issues particularly due to their fragility at small thicknesses. Furthermore, technology roadmaps related to chip packaging require integration of passive circuit elements (e.g., resistors, capacitors) into interposers.
A need therefore exists for a methodology enabling incorporation of small area, thin, light, cost-efficient, reliable, and robust Circuit Board Assemblies (CBAs) in wearable devices, IOT-interconnected devices, as well as interposers used in 2.5D/3D packaging markets, and the resulting devices.